multiple interfaces accessing the same uvm_reg
Multiple interfaces( processor 0 ,processor 1, processor 2) do write/read the same register. I created p0_map, P1_map, P2_map and set different sequencers in environment....
View ArticleWhy doesn't this virtual interface connection crash and burn
Hi Everyone, I got some strange code (at least strange to me) from a college of mine and I can not understand why it works, reading the code I expect the tools to fail at compilation and elaboration...
View ArticleMultiple architectures - which one?
I am relatively new to UVM, and I'm trying to think through the architecture of a transaction. Assume that in this case, I have the ability to modify the object under discussion directly. I have a...
View ArticleControlling timescale with set_timeout
What is the recommended way to control the timescale of the UVM timeout as set with set_timeout()? Controlling the timescale in the calling code doesn't seem to work. For example, `timescale...
View ArticleUVM RAL - Register Verification for Different Access types
I'm experimenting UVM RAL register verification for all the access types for registers and I'm experiencing the issue while using built-in sequence uvm_reg_access_seq. In my design I've implemented all...
View Articlehandle to uvm_component in uvm_object
Hi, Is there a way to avoid the "complex type usage" error when needing to feed a uvm_object a handle to an uvm_component? What I need to do is access within a sequence a method of one component in...
View Articlebuild_phase order
Hi, I notice something interesting in the build_phase order of uvm_component. The uvm_component at the same level are build in the alphabetatical order of the instance name. I expect the build order...
View ArticleUVM Sequencer base class - Virtual task using local class variables - bad...
I see uvm_sequencer_base::wait_for_grant (UVM 1.1d) is a virtual task but accesses a local int g_request_id - is this not a bad coding style? If I were to override this virtual method for debug with...
View Articlemultiple maps on ral class
Hi, We are using snps ralgen to generate the regmodel. It appears that the ralgen creates only the default map. We would like to have 2 maps for 2 separated if masters. Is there an online example for...
View Articlepriority for uvm_reg transactions
There are many threads/virtual sequences in the test that will initiate register transactions through a shared register model/bus agent. I want to give specific sequences higher priority so they will...
View ArticleUsage of get_hdl_path() for backdoor register access
Hi All, I wanted to know the usage of get_hdl_path() and get_full_hdl_path(). Any example would be helpful. I have added set_hdl_path_root for register block on top level and added add_hdl_path for...
View ArticleWhat is a proper way to set fields and update register in uvm register model?
In my test sequence, some fields of a register are changed frequently and others are keep previous value. I wrote the code like below, register.fieldY.set(value) register.update(status) // first...
View ArticleTurn off `uvm_info messages
Is there any way to turn off `uvm_info messages being displayed on the log while retaining `uvm_error and `uvm_fatal messages
View ArticleCommunication between uvm_sequence and uvm_component
I have two classes, one is block_seq which extends from uvm_sequence and other is block_cfg_mngr which extends from uvm_component. How do I exchange information between these two. I need to generate...
View ArticleRAL mapping reg_field to another reg_field
Hey! I'm think need some help with RAL. I have 2 registers and in reg A field F1(RO) mapped from reg B field F1(RW) how i must implement this using RAL?
View ArticleQuery related to UVM_RAL_REG model.
I have query related to UVM_RAL model. Does it support for case-insensitive for accessing Registers and Register fields items from UVM_RAL model? For example. We have testcase with extension of...
View ArticleInstance override RAL adapter transaction objects?
Hello, We have a test bench environment where we have 2 objects of the same SPI env class. The SPI env sets the sequencer for the RAL model as follows:...
View ArticleWhy we get SEQREQZMB when jumping to another phase
I have a reset sequence, which starts as default_sequence for reset_phase. For main_phase I have some sequence, which is started as default sequence. At some time I jump from main_phase to reset_phase....
View ArticleComplicated Register Modeling with uvm_reg
Looking for suggestions on the best approach to modeling something akin the following. data bus width: 16 bits addr bus width: 16 bits register: cfg @ 0xa000 field: value_mode @ 0 : enum {...
View ArticleAre there any recommendations/guidelines on using UVM run sub phases?
The cook book from Mentor tells following and in another thread, the moderator also suggested against using the sub phases of run. However in one of my projects, I do find the need for using them (and...
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