Quantcast
Channel: UVM Methodology and BCL Forum RSS Feed
Viewing all 283 articles
Browse latest View live

uvm register implimentation for same register with different instances

$
0
0

Hello , 

 

  I have a scenario as below , 

 

In the dut , there is a set of registers which acts as control register for different instances of same IP inside dut. There is a control register which controls the set of registers to decide which instance of IP it needs to wr/rd .

 

I am thinking of creating a reg block for the set of registers and instantiate as per the IP instance number. But I am not sure how the reg wr/rd of each block as per the control register IP selection . Please comment on this problem . 

 

Thanks


How do I raise objection to main phase in a component's run_phase()

$
0
0

In the run_phase() of a component, I'd like to raise an objection to the main phase so I added the following:

 

uvm_main_phase::get().raise_objection(this);

 

and I get this error when it runs:

 

        UVM_ERROR @ 0 ns: reporter [UVM/PH/NULL_OBJECTION] 'uvm_test_top.foo' attempted to raise an objection on 'main', however 'main' is not a task-based phase node!  (This is a UVM_PHASE_IMP, you have to query the schedule to find the UVM_PHASE_NODE)

 

Why?  What do I not understand or how should this be done?  

 

It looks to me like uvm_main_phase is derived from uvm_task_phase so wouldn't that make it a "task-based phase node"?

 

Thanks.

 

Walker

 

referring/connecting env in a test

$
0
0

Hi,

 

Following is the sample code

 

class a_env extends uvm_env

....

endclass

 

class basic_test extends uvm_test

 

a_env a_env1;

a_env1 = a_env::type_id:create("a_env", this);

 

endclass

 

class b_env extends uvm_env

a_env a_env2; // only reference

 

...

endclass

 

class my_test extends basic_test

b_env b_env1;

 

 

virtual function void connect_phase( umv_phase phase)

  super.connect_phase(phase);

  b_env1.a_env2 = a_env1;

endfunction

..

endclass

 

 

I am getting NULL_OBJCT access error with the above code..  can anyone helpout?

 

Thanks,

Satya

Transaction Recording in Cadence

$
0
0

Hi All,

I have enabled transaction recording in my UVM TB using begin_tr() and end_tr() macros in my uvm_driver and I am able to see the bubble in the waveform.
But the bubble is not in sync with the time frame when the transaction is passed, Could anyone help me with a reason or solution to this?

Thanks,
Leela

Simulation speed/efficiency

$
0
0

I would like to hear your best practices for ensuring simulation efficiency.  I'm open to all ideas; the profiler in my tool is nightmare to make sense of.

 

I'm especially interested in...

good coding practices

checks for incorrect garbage collection, etc (if such a thing exists)

etc.

 

Thanks!

Say, you got a nice forum.Thanks Again. Really Great. Heikkila

$
0
0
Say, you got a nice forum.Thanks Again. Really Great. Naz

Test / Sim Farm

$
0
0

A coworker and I were discussing this question...

 

In order to run a regression suite, or multiple regression suites, etc, would you...

 

run a test, stop the simulator, log any results (pass/fail), etc, then start the simulator again on a new test with a new random seed

 

OR...

 

Run a single test, which runs several high level sequences, one after the other?

How to change verbosity of message during simulation?

$
0
0

Hi,

 

I want to change the verbosity  of the message during simulation through "uvm_report_catcher". I used "set_verbosity" method and changed all UVM_LOW verbosity to UVM_FULL.

I ran test with UVM_MEDIUM verbosity but all messages declared with UVM_LOW verbosity are printed in the log file.

 

I have pasted an example in which there are some messages in "tb_env" class with UVM_LOW, UVM_MEDIUM and UVM_HIGH verbosity and the verbosity UVM_LOW is changed to UVM_HIGH. I ran this example with UVM_MEDIUM verbosity. But as shown in output, messages with UVM_LOW verbosity are printed.

 

Example:

program test;

import uvm_pkg::*;
`include "uvm_macros.svh"

class tb_env extends uvm_env;
   `uvm_component_utils(tb_env)

   function new(string name, uvm_component parent = null);
      super.new(name, parent);
      `uvm_info(get_full_name(),"Env class new function completed", UVM_HIGH)
   endfunction

   function void build_phase(uvm_phase phase);
      uvm_config_db#(time)::set(null, "global_timer.*",    "timeout", 1000);
      uvm_config_db#(time)::set(null, "global_timer.main", "timeout", 3000);
      uvm_config_db#(time)::set(null, "global_timer.run",  "timeout", 0);
      `uvm_info(get_full_name(),"Env class build function completed", UVM_HIGH)
   endfunction

   
   task reset_phase(uvm_phase phase);
      `uvm_info(get_full_name(),"Env class reset_phase started", UVM_LOW)
      phase.raise_objection(this);
      #20;
      phase.drop_objection(this);
      `uvm_info(get_full_name(),"Env class reset_phase completed", UVM_MEDIUM)
   endtask
   
   task configure_phase(uvm_phase phase);
      `uvm_info(get_full_name(),"Env class configure_phase started", UVM_LOW)
      phase.raise_objection(this);
      #200;
      phase.drop_objection(this);
      `uvm_info(get_full_name(),"Env class configure_phase completed", UVM_MEDIUM)
   endtask
   
   task main_phase(uvm_phase phase);
      `uvm_info(get_full_name(),"Env class main_phase started", UVM_LOW)
      phase.raise_objection(this);
      #1000;
      phase.drop_objection(this);
      `uvm_info(get_full_name(),"Env class main_phase completed", UVM_MEDIUM)
   endtask

   task shutdown_phase(uvm_phase phase);
      `uvm_info(get_full_name(),"Env class shutdown_phase started", UVM_LOW)
      phase.raise_objection(this);
      #10;
      phase.drop_objection(this);
      `uvm_info(get_full_name(),"Env class shutdown_phase completed", UVM_MEDIUM)
   endtask
endclass

tb_env env;

class test1_demoter extends uvm_report_catcher;
  `uvm_object_utils(test1_demoter)
  function new(string name="test1_demoter");
    super.new(name);
  endfunction
  function action_e catch();
    if(get_severity() == UVM_INFO) begin
      set_severity(UVM_WARNING);
      `uvm_info("demoter", "Caught FATAL / demoted to ERROR", UVM_MEDIUM)
    end
    if(get_verbosity() == 100) begin
      set_verbosity(400);
      `uvm_info("demoter","Changing verbosity",UVM_LOW)
    end
    return THROW;
  endfunction
endclass

class test extends uvm_test;
   test1_demoter demoter;
   `uvm_component_utils(test)
   function new(string name, uvm_component parent = null);
      super.new(name, parent);
      `uvm_info(get_full_name(),"Test class new function completed", UVM_HIGH)
   endfunction

   function void build_phase(uvm_phase phase);
     super.build_phase(phase);
    env     = tb_env::type_id::create("env",this);
    demoter = test1_demoter::type_id::create("demoter");
    uvm_report_cb::add(env, demoter);
      `uvm_info(get_full_name(),"Test class build function completed", UVM_HIGH)
   endfunction

   task pre_main_phase(uvm_phase phase);
      phase.raise_objection(this);
      #100;
      phase.drop_objection(this);
   endtask
   
   task main_phase(uvm_phase phase);
      phase.raise_objection(this);
      // Will cause a time-out
      // because we forgot to drop the objection
   endtask
   
   task shutdown_phase(uvm_phase phase);
      phase.raise_objection(this);
      #100;
      phase.drop_objection(this);
   endtask
endclass


initial
begin
   run_test("test");
end

endprogram

 

 

Command:  vsim -sv_lib ../../../../lib/uvm_dpi -c "+UVM_VERBOSITY=UVM_MEDIUM" -do "run -all; q" -l questa.log -f questa.tops

 

Output:

 

# run -all
# UVM_INFO ../../../../src/base/uvm_root.svh(392) @ 0: reporter [UVM/RELNOTES]
# ----------------------------------------------------------------
# UVM-1.2
# © 2007-2014 Mentor Graphics Corporation
# © 2007-2014 Cadence Design Systems, Inc.
# © 2006-2014 Synopsys, Inc.
# © 2011-2013 Cypress Semiconductor Corp.
# © 2013-2014 NVIDIA Corporation
# ----------------------------------------------------------------
#
#   ***********       IMPORTANT RELEASE NOTES         ************
#
#   You are using a version of the UVM library that has been compiled
#   with `UVM_NO_DEPRECATED undefined.
#   See http://www.eda.org/svdb/view.php?id=3313 for more details.
#
#   You are using a version of the UVM library that has been compiled
#   with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
#   See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
#       (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO @ 0: reporter [RNTST] Running test test...
# UVM_INFO test.sv(87) @ 0: uvm_test_top.env [demoter] Caught FATAL / demoted to ERROR
# UVM_INFO test.sv(91) @ 0: uvm_test_top.env [demoter] Changing verbosity
# UVM_WARNING test.sv(45) @ 0: uvm_test_top.env [uvm_test_top.env] Env class reset_phase started
# UVM_INFO test.sv(87) @ 20: uvm_test_top.env [demoter] Caught FATAL / demoted to ERROR
# UVM_WARNING test.sv(49) @ 20: uvm_test_top.env [uvm_test_top.env] Env class reset_phase completed
# UVM_INFO test.sv(87) @ 20: uvm_test_top.env [demoter] Caught FATAL / demoted to ERROR
# UVM_INFO test.sv(91) @ 20: uvm_test_top.env [demoter] Changing verbosity
# UVM_WARNING test.sv(53) @ 20: uvm_test_top.env [uvm_test_top.env] Env class configure_phase started
# UVM_INFO test.sv(87) @ 220: uvm_test_top.env [demoter] Caught FATAL / demoted to ERROR
# UVM_WARNING test.sv(57) @ 220: uvm_test_top.env [uvm_test_top.env] Env class configure_phase completed
# UVM_INFO test.sv(87) @ 320: uvm_test_top.env [demoter] Caught FATAL / demoted to ERROR
# UVM_INFO test.sv(91) @ 320: uvm_test_top.env [demoter] Changing verbosity
# UVM_WARNING test.sv(61) @ 320: uvm_test_top.env [uvm_test_top.env] Env class main_phase started
# UVM_INFO test.sv(87) @ 1320: uvm_test_top.env [demoter] Caught FATAL / demoted to ERROR
# UVM_WARNING test.sv(65) @ 1320: uvm_test_top.env [uvm_test_top.env] Env class main_phase completed
# UVM_FATAL ../../../../src/base/uvm_phase.svh(1491) @ 9200000000000: reporter [PH_TIMEOUT] Default timeout of 9200000000000 hit, indicating a probable testbench issue
# UVM_INFO ../../../../src/base/uvm_report_catcher.svh(705) @ 9200000000000: reporter [UVM/REPORT/CATCHER]
# --- UVM Report catcher Summary ---
#
#
# Number of demoted UVM_FATAL reports  :    0
# Number of demoted UVM_ERROR reports  :    0
# Number of demoted UVM_WARNING reports:    0
# Number of caught UVM_FATAL reports   :    0
# Number of caught UVM_ERROR reports   :    0
# Number of caught UVM_WARNING reports :    0
#
# UVM_INFO ../../../../src/base/uvm_report_server.svh(847) @ 9200000000000: reporter [UVM/REPORT/SERVER]
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO :   12
# UVM_WARNING :    6
# UVM_ERROR :    0
# UVM_FATAL :    1
# ** Report counts by id
# [PH_TIMEOUT]     1
# [RNTST]     1
# [UVM/RELNOTES]     1
# [UVM/REPORT/CATCHER]     1
# [demoter]     9
# [uvm_test_top.env]     6
#
# ** Note: $finish    : ../../../../src/base/uvm_root.svh(135)
#    Time: 9200 sec  Iteration: 0  Region: /uvm_pkg::uvm_phase::execute_phase
# End time: 11:59:34 on Nov 06,2015, Elapsed time: 0:00:04
# Errors: 0, Warnings: 0
 


Random stability issue with `uvm_info and changing verbosity

$
0
0

I've encountered a rather nasty issue with the UVM 1.2 BCL where changing the `uvm_info verbosity from UVM_NONE to UVM_LOW for the same random seed yields different simulation results.

 

Mantis bug logged here:

https://accellera.mantishub.com/view.php?id=5482

 

This is not good practice, BUT - It is possible for the random stability to be affected, for example, if within the `uvm_info macro, a function is called that allocates a new object or randomizes, thus altering the RNG.

 

Example:

 

`uvm_info("SOME_ID", $psprintf("Some number is: %0d", get_some_number()), UVM_LOW)

 

function int get_some_number();

  some_object obj = new();

  get_some_number = $urandom;

endfunction

 

I understand that some effort has been put in to revamping the message reporting mechanism from 1.1 to 1.2, as well as improving the random stability with the insertion of get/set_randstate guards.

 

If this is something that is completely unavoidable in UVM, then it might be a good idea to add this to the UVM User Guide as an example of bad coding.

 

 

 

uvm_reg::write updates regmodel in explicit prediction mode

$
0
0

When using UVM register layer with predictor and bus adapter, in explicit prediction mode(implicit prediction disabled by setting auto_predict to 0),  uvm_reg::write task directly updates register model value(mirror register), at the same moment when write task is called before transaction is completed on the bus interface.

In explicit prediction mode, uvm_reg::write should only launch transaction on bus agent, then predictor will wait for transaction to be collected by bus monitor and only then update regmodel.

This worked well in UVM-1.0. but it doesn't work from UVM-1.1.

 

Inside uvm_reg::write task, unconditional call of set(value) function has been added in UVM-1.1, and this function updates regmodel value regardless the auto_predict setting.

uvm_reg::write in UVM-1.0 had only call of do_write() at the end, which takes into account auto_predict mode setting.

 

 

Has someone else noticed this issue? Is this known bug in UVM register layer?

 

Regards,

Alex

 

 

task uvm_reg::write(output uvm_status_e      status,
                    input  uvm_reg_data_t    value,
                    input  uvm_path_e        path = UVM_DEFAULT_PATH,
                    input  uvm_reg_map       map = null,
                    input  uvm_sequence_base parent = null,
                    input  int               prior = -1,
                    input  uvm_object        extension = null,
                    input  string            fname = "",
                    input  int               lineno = 0);

   // create an abstract transaction for this operation
   uvm_reg_item rw;

   XatomicX(1);

  
set(value);

   rw = uvm_reg_item::type_id::create("write_item",,get_full_name());
   rw.element      = this;
   rw.element_kind = UVM_REG;
   rw.kind         = UVM_WRITE;
   rw.value[0]     = value;
   rw.path         = path;
   rw.map          = map;
   rw.parent       = parent;
   rw.prior        = prior;
   rw.extension    = extension;
   rw.fname        = fname;
   rw.lineno       = lineno;

  
do_write(rw);

   status = rw.status;

   XatomicX(0);

endtask

 

 

uvm_component apply_config_settings method limitation

$
0
0

Hi All,

 

It seems that there is a problem for automatically updating components fields registered with uvm_field_* macros.

It works fine if the field is of type int, but it fails if the field is of type enum.

Do I miss something?

(I tested this code with both UVM 1.1-d and UVM 1.2)

 

class hs_driver extends uvm_driver #(hs_packet);

   hs_type_t driver_type;
   int       my_param = 10;
  
   `uvm_component_utils_begin (hs_driver)
      `uvm_field_enum (hs_type_t, driver_type, UVM_ALL_ON)
      `uvm_field_int (my_param, UVM_ALL_ON)
   `uvm_component_utils_end
  [...]

endclass: hs_driver

class test_bench extends uvm_component;
   `uvm_component_utils (test_bench)

   hs_driver host;
   hs_driver device;
   
  [...]

   virtual function void build_phase(uvm_phase phase);
      super.build_phase(phase);
      uvm_config_db#(hs_type_t)::set (null, "*.device", "driver_type", DEVICE);
      uvm_config_db#(int)::set (null, "*.host", "my_param", 888);

      host = hs_driver::type_id::create ("host", this);
      device = hs_driver::type_id::create ("device", this);
   endfunction: build_phase
   
endclass: test_bench


Printing test topology:

-------------------------------------------------------------
Name                      Type                    Size  Value
-------------------------------------------------------------
uvm_test_top              simple_test             -     @1863
  mtb                     test_bench              -     @1939
    device                hs_driver               -     @2089
      rsp_port            uvm_analysis_port       -     @2162
        recording_detail  integral                32    'd1  
      seq_item_port       uvm_seq_item_pull_port  -     @2130
        recording_detail  integral                32    'd1  
      driver_type         hs_type_t               32    HOST -> should have been DEVICE!
      my_param            integral                32    'ha  
      recording_detail    integral                32    'd1  
    host                  hs_driver               -     @2024
      rsp_port            uvm_analysis_port       -     @2095
        recording_detail  integral                32    'd1  
      seq_item_port       uvm_seq_item_pull_port  -     @2058
        recording_detail  integral                32    'd1  
      driver_type         hs_type_t               32    HOST
      my_param            integral                32    'h378 -> In this case (for an integer) the field has been updated followin uvm_config_db
      recording_detail    integral                32    'd1  
    recording_detail      integral                32    'd1

uvm_config_db and hierarchical access

$
0
0
c4brian and I have messaged a bunch about ways to share data and access between elements in SV/UVM code.
I put common functions/tasks/constants into a package, which I think is standard.
I realize that absolute dot notation of accessing elements (i.e.  variable12 = smthgA.smthgB.smthgC.variableXYZ;) is frowned upon as it is not good for reuse.
So, the UVM presents the uvm_config_db to facilitate reuse and simplify connectivity across a hierarchy.**1
 
Many folks have (including c4brian, I believe) commented that they don't like how verbose it is to ::get from the config db and to check the return result.
   if (! uvm_config_db#(integer)::get(this,"hiccup","xyz_important_var", important_var) ) begin
     `uvm_fatal("ERROR,"important_var not found in config_db")
   end 
In a recent testbench, I've done the following. I probably need to review how the config component is supposed to be used.
I am curious what others think.
 
My setup:
1) Create an object to store common variables and handles.
//This should be a singleton and serve as a central point for others to access global connections. Likely not a good style.  Discuss.
class xyz_config extends uvm_component;
   `uvm_component_utils(xyz_config)

   static xyz_env          m_env;
   static id_state         m_id_state;
   static delay_ctl        m_delayctl;

   function new(string name="xyz_config", uvm_component parent=null);
      super.new(name, parent);
   endfunction

set_env_handle(input xyz_env handle);
   m_env=handle;
endfunction : set_env_handle

...
2) When something is created that other code might want to access, I set a handle to it in xyz_config.
ex1: In the test class constructor (which is declared inside top), create the env and set a handle to it in the xyz_config.  (Probably these actions should be done in the build_phase rather than the constructor.)
class test_base extends uvm_test;
   `uvm_component_utils(test_base)

   xyz_env env;

   function new(string name = "test_base", uvm_component parent = null);
      super.new(name, parent);
      env = xyz_env::type_id::create("env",this);
      rrc_config::set_env_handle(env);

ex2: In the env build_phase, I set handles to some objects which track data which is useful in many sequences and other code

function void xyz_env::build_phase(uvm_phase phase);
   super.build_phase(phase);
  ...

   // Create Helper Structures
   m_id_state = id_state::type_id::create("m_id_state",this);
   xyz_config::set_id_state_handle(m_id_state);
   m_delayctl = delay_ctl::type_id::create("m_delayctl",this);
   xyz_config::set_delayctl_handle(m_delayctl);
3) Now, in various parts of the tb (such as from sequences), I can access xyz_config as a singleton, and access its handles (using . "dot" notation) to whatever data structures it was given access to.  (I'm thinking now that those data structures should be in the scoreboard.)

The dot notation is much more concise than declaring a variable and then performing a uvm_config_db ::get and checking the return value. 

//in seq, id_state which tracks system-state used to set transaction variable
jhg_input_trans.state = xyz_config::m_id_state.get_jhg_state(.loopback(loopback), .fce_1(fce_1));
or
//in virtual seq, a call is made that turns off any internal stallers (special stallers to alter congestion in the dut)
xyz_config::m_env.turn_off_internal_stallers();
or
//in scoreboard, as monitors send in transactions, it adjusts state info which is used by sequences to make legal input
xyz_config::m_id_state.move_some_id(.note("fuf->xyz"), .syd(t.fuf_xyz_read_syd), .from_q(Q001), .to_q(Q111));

A benefit of this is that the user can more easily (from this line of code), see what is being accessed, rather than needing to rerun a test and dump config_db or grep thru a bunch of files to see who did the ::set.

With regards to reuse, it seems to me that as long as the new tb (that wants to benefit from reuse), sets the handles in the _config properly, it is just as reuse-able.

 

Probably, I am missing something.

 

 
I've have a vague notion and have heard soft feedback that this style (which I feel is unique to me) is not good.  Maybe I'm imagining this or exaggerating it in my mind.  I bring it up here, in the event anyone has feedback or a good scolding to give.
 
 
**1
  Conceptually I've been taught to think of uvm_config_db as a "string"-accessible associative array, or a group of associative arrays; something like 'one for each datatype'.
  I'm not poking into the uvm base class here, but just voicing my understanding out-loud for comments.  Conceptually, I think of uvm_config_db as operating as follows.
A user specifies the data type that they want to store or get - which 'conceptually' selects which associative array to access.
A user specifies a "string-name" which is the key into that associate array.
A user reads or writes that associative array as follows.
  To write, they use ::set,  specify a "string-name",  and provide a value.
  To read, they use ::get, specify a "string-name", and provide a variable, into which the value stored at "string-name" will be copied.
 
(Note: I've modified the code examples to shorten them, so may have introduced typos.)

my test stuck in uvm sequence `uvm_send()

$
0
0

when I run a test case by UVM

 

I found that the case stuck in `uvm_send()  it can not print the log behind uvm_send

 

maybe the connection is wrong or disconnect between sequencer and driver , so that the driver's " seq_item_port.try_next_item(req) " will always get NULL

 

right?

 

so how can I fix this problem?

 

Thanks a lot!!!

 

 

 

 

Adding a run-time phase example

$
0
0

I'm sure it's simple (if you know what you're doing) but could someone please point me to, or include in a response, a simple and complete example of defining a user-defined phase to be inserted into the schedule between the pre_configure and configure phases?

 

Thanks.

 

Uvm filed macro

$
0
0

Hi,

 

I have an associative array of enum indexed by an integer. 

 

I am unable to figure out the filed macro for the factory operations. 

 

Can someone help me with it  :) .

 

Thanks,

Nik


Enabling inbuilt UVM RAL coverage sampling

$
0
0

Hi,

 

I want to use in-built UVM RAL cover groups.

I tried following steps but did not help :

 

1) Enable coverage building:

     Before building register model, I use following :

     uvm_reg::include_coverage("*",UVM_CVR_ALL);

 

2) To enable sampling :

    <_regmodel>.set_coverage(UVM_CVR_ALL);

 

In my regmodel there are two types of cover groups: UVM_CVR_ADDR_MAP in top level register model and UVM_CVR_REG_BITS in individual registers.

 

I was hoping that UVM_CVR_ALL would enable sampling of all.

 

I could see cover groups getting built but are not sampled.

 

Am I missing something ?

 

Please let me know.

 

Thanks.

RAL. Mirroring registers with the same addresses

$
0
0
I have DUT which contains 2 registers (A and B ) with the same addres. DUT also has the third register © which control to what register write: to A or to B.

Using RAL we have problems with mirroring registers A and B, because they have the same physical addres.
How caw we solve it?

I found a way which works:
1) give registers A and B unique addresses
2) make register adapter to change address using register C

Selection of specific physical interface in default UVM register layer sequences

$
0
0

In our DUT, we have two separate independent physical interfaces (APB & I2C) (active 1 at a time) through which all registers can can be accessed,

 

Also in our register model, we created two reg_maps, one for each APB & I2C.
 
Now through testcase, we want only one physical interface at a time, to be subjected to default uvm sequences (i.e. uvm_reg_access_seq, uvm_reg_bit_bash_seq,etc) but it is not possible as uvm_sequence will get all the maps using get_maps();

 

  So without over-riding the default uvm_reg_access_seq, is it possible to achieve such type of configuration in testcase itself via using uvm_reg_map or some other methods.

 

Kindly refer following pseudo code

//Pseudo Code for Scenario
 class  dut_reg_test extends base_test;
  `uvm_component_uti ls(dut_reg_test)
  
  //Handle of default uvm register access sequence
  uvm_reg_access_seq my_reg_seq;
  // Select Physical Interface
  rand bit APB_I2C;
   
  uvm_reg_map test_map;
  dut_reg_model regmodel;
  
  task buid_phase (uvm_phase phase);
    super.build_phase(phase);
    // Select PHY Interface via commandline
      if ($value$plusargs("APB_I2C=%b", APB_I2C))
     else
        APB_I2C = $random;
    
    if (APB_I2C)
       test_map = regmodel.apb
    else
       test_map = regmodel.i2c
  endtask : build_phase

   task main_phase (uvm_phase phase); 
    //Create method for sequence
    my_reg_seq=uvm_single_access_seq::type_id::create("my_reg_seq");
    //Randomize with selected map
    my_reg_seq.randomize with { maps == test_map;});
    // Start default sequence
     my_reg_seq.start(NULL);
   endtask : main_phase
  
endclass : dut_reg_test

The above strategy cannot be implemented because uvm_reg_access sequence doesn't contain uvm_reg_map it's only present in uvm_reg_single_access_seq,

 

Similar kind of limitations persists will all uvm_reg_bit_bash_seq & reset sequences.

 

Can we have some strategy to resolve this issue ?

 

Thanks :)

Nikunj Hinsu

 

 

Virtual Sequencer :: Sequencer Arbitration

$
0
0

Hi,

Can we use Sequencer arbitration on the Virtual sequencer ? If so, how does this arbitration affect the sub_sequencers? Also, Can someone please clarify?

 

The UVM sequencer has six arbitration modes:
• UVM_SEQ_ARB_FIFO (default)
• UVM_SEQ_ARB_RANDOM
• UVM_SEQ_ARB_STRICT_FIFO
• UVM_SEQ_ARB_STRICT_RANDOM
• UVM_SEQ_ARB_WEIGHTED
• UVM_SEQ_ARB_USER

 

Regards,
Santosh

 

receiving null pointer error when accessing config object from uvm_do_with

$
0
0

Hi,

 

i have an agent (uvm_agent) which has a config object (uvm_object) which holds the agent's configurations.

i am setting this config from the environment and getting it inside the agent.

in the agent i am setting this config for everyone to see (*).

 

i have a sequence for this object that get's this config object.

everything works ok so far and i am able to access all the configurations from the config object inside the sequence.

the problem starts when i try to create constrained transactions (`uvm_do_with) with the constraints taken from this config object.

then i get a null pointer error.

 

the error:

 
Error-[CNST-NPE] Constraint null pointer error
/space/users/assafg/nu4000/verification/iae/ciif_agent/ciif_sequence.sv, 194
  Accessing null pointer cfg.frame_width in constraints.
  Please make sure variable cfg.frame_width is allocated.
 

so i can access a certain field from the sequence but when i try to set it as a constraint i get an error.

 

some code from the sequence (this is only part of the code):

 

    virtual task pre_start();
        // Get the configuration
        if (!uvm_config_db #(ciif_cfg)::get(get_sequencer(), "", "cfg", cfg)) begin
            `uvm_fatal("CFGERR", "%m cfg not set")
        end
    endtask: pre_start
 
 
    virtual task body();
        `uvm_info("DEBUG_DEBUG", $sformatf("cfg.frame_width = %0d\n", cfg.frame_width), UVM_NONE);                 // print occurs and proves that i can access this field
       
        `uvm_do_with(req, {
                                            fwidth  == cfg.frame_width;             // error here
                                       }
                               );
    endtask: body
 
 
any idea would be much appreciated.
 
Thanks,
Assaf
 

 

 

 

Viewing all 283 articles
Browse latest View live