Hi all,
How to end simulation when there are forever-loops in sub-sequence and monitor? I have tried set_drain_time, but it doesn't work. If I remove the forever-loops in sub-sequence and monitor. The simulation ends when drop_objection executes done successfully in top-sequence after all the item being sent. By the way, I want to monitor signals of DUV during all the simulation time until the last item being sent. Could anybody tell me the trick? Thanks in advance.
Hi all,
There is one register model such as this:
class R_r extends uvm_reg; uvm_reg_field vaule; ... endclass : R_r
class A_R_file extends uvm_reg_file; R_r R; ... endclass : A_R_file
class R_model extends uvm_reg_block; A_R_file R_f; ... endclass : R_model
class my_r_seq extends uvm_reg_sequence; R_model regmodel; ... write_reg(regmodel.R_f.R, status, wdata); peek_reg (regmodel.R_f.R, status, rdata); ... endclass : my_r_seq
R_r is write-only, when reading R_r via backdoor as above, VCS reports such an error.
Hello,
I am using the uvm_heartbeat object in my test bench and found that it always watches for all objection activity under the context component. By definition, it should only watch for the list of components registered to it. I found this when registering only one component to watch (my interrupt handler) and even after the component had no activity long after several heartbeat windows, a fatal HBFAIL message was not issued.
Digging into the source code, I can see that the heartbeat keeps track of which components are registered by populating an associative array, like this:
function void set_heartbeat (uvm_event e, ref uvm_component comps[$]); uvm_object c; foreach(comps[i]) begin c = comps[i]; if(!m_cb.cnt.exists(c)) // <-- This is the code to track... m_cb.cnt[c]=0; // <-- which components are registered if(!m_cb.last_trigger.exists(c)) m_cb.last_trigger[c]=0; end if(e==null && m_event==null) return; start(e); endfunction
Skipping forward to the uvm_heartbeat_callback class, a counter is incremented every time a component raises or lowers an objection. When a component isn't found in the "cnt" associative array, it should have ignored it, but instead it sets a new index and sets the value to 0:
virtual function void raised (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); if(obj == target) begin if(!cnt.exists(source_obj)) cnt[source_obj] = 0; // <-- this is the bug cnt[source_obj] = cnt[source_obj]+1; // <-- BTW: isn't cnt[source_obj]++ faster? last_trigger[source_obj] = $realtime; end endfunction
Instead, the code should have been written like this:
virtual function void raised (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); if(obj == target) begin if(!cnt.exists(source_obj)) return; // <-- bug fix cnt[source_obj]++; // <-- (seems like it should be faster) last_trigger[source_obj] = $realtime; end endfunction
I have tried this change in my workspace and it works well.
Thank you,
David
Hi all,
There are such codes in heartbeat class:
virtual task run_phase(uvm_phase phase);
uvm_callbacks_objection cb;
uvm_heartbeat hb;
uvm_event e;
uvm_component comps[$];
if (heartbeat_window == 0) begin
return;
end
e = new("e");
assert($cast(cb, phase.get_objection()))
else
`uvm_fatal("heartbeat", run_phase objection isn't the type of uvm_callbacks_objection. You need to define UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE!)
hb = new(get_full_name(), m_context, cb);
uvm_top.find_all("*", comps, m_context);
hb.set_mode(UVM_ANY_ACTIVE);
hb.set_heartbeat(e, comps);
fork
forever begin
#heartbeat_window e.trigger();
end
join_none
endtask: run_phase
The VCS always reports assertion fail even though I defined UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE in define.svh or in command line.
The way of defining UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE:
in define.svh
in command line:
VCS = vcs -sverilog -debug_all -picarchive -timescale=1ns/1ps \
+acc +vpi \
+define+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR+UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE \
If I defined UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE, phase.get_objection() should return the uvm_callbacks_objection type and the assert should be successful, but it doesn't. Why?
Thanks in advance!
Hi all,
There are such codes in heartbeat class:
virtual task run_phase(uvm_phase phase);
uvm_callbacks_objection cb;
uvm_heartbeat hb;
uvm_event e;
uvm_component comps[$];
if (heartbeat_window == 0) begin
return;
end
e = new("e");
assert($cast(cb, phase.get_objection()))
else
`uvm_fatal("heartbeat", run_phase objection isn't the type of uvm_callbacks_objection. You need to define UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE!)
hb = new(get_full_name(), m_context, cb);
uvm_top.find_all("*", comps, m_context);
hb.set_mode(UVM_ANY_ACTIVE);
hb.set_heartbeat(e, comps);
fork
forever begin
#heartbeat_window e.trigger();
end
join_none
endtask: run_phase
The VCS always reports assertion fail even though I defined UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE in define.svh or in command line.
The way of defining UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE:
in define.svh
in command line:
VCS = vcs -sverilog -debug_all -picarchive -timescale=1ns/1ps \
+acc +vpi \
+define+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR+UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE \
If I defined UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE, phase.get_objection() should return the uvm_callbacks_objection type and the assert should be successful, but it doesn't. Why?
Thanks in advance!
I'm trying to figure out how to get uvm_reg to do register reads over a bus like PCIe, where the read command is decoupled from the read data. In other words, one transaction on the bus is sending the read command to the DUT (a mem_read TLP, in the PCIe example), and then some indeterminate time later, the response to that read comes as another transaction from the DUT back to the testbench (a completion TLP in PCIe). uvm_reg seems to assume the simple case where a sequence can call start_item, finish_item, and then the read data has been placed in the original transaction by the driver. In our agent, the driver is not involved with completions from the DUT at all, the monitor is.
Hi All,
I am new to UVM methodology. I have gone through UVM class reference manual. As, UVM is an open source method used by whole verification industry, Run time performance verification and power aware verification can be standardize with providing components for those verification in library.
Performance measurment can be standardize for bandwidth utilization, effective throughput and internal delay calculation. It can be both combination of checker component calcualtion at run time and timers to calculate the difference between start and stop timers to calculate bandwidth in Transfers/Second.
Also, Nice reporting table can be added for generating performace reporting for all buses at one place.
People can inherrit the base class and modify the usage as needed.
Regards,
Rakesh Sachdev
why do we have the base class as uvm_void in uvm library even though it doesn't have any variables or functions?
what purpose does it serve?
Hi All,
I am getting following error message while using `uvm_object_utils to register a sequence :
1) m_do_cycle_check is not a class item
2) Expecting a function name
3) m_uvm_cycle_scopes is not a class item.
Please let me know if any one knows about these issues.
Thanks and Regards,
GG
Is there some reason uvm_tim_time is not derived from uvm_object? It contains just the sort of timescale neutral API I was looking for, so I added it to a class I'm developing. I'm not able to use the `uvm_field_object() macro with this uvm_tlm_time object, because it lacks some of the expected functions. I suppose I could extend it and add those functions, or I could just not use the macro. But this seems strangely inconsistent.
-Ryan
Hi all,
I'm facing an issue when using the UVMconnect package.
The simulator complains about missing fields:
# ** Error: (vsim-3567) /share/uvmc-2.2//src/connect/sv/uvmc_tlm1.sv(652): No field named 'm_get_if_mask'.
# Region: /uvmc_pkg::uvmc_tlm1_port_proxy::uvmc_tlm1_port_proxy__1
# ** Error: (vsim-3567) /share/uvmc-2.2//src/connect/sv/uvmc_tlm1.sv(652): No field named 'm_get_if_mask'.
# Region: /uvmc_pkg::uvmc_tlm1_port_proxy::uvmc_tlm1_port_proxy__1
# ** Error: (vsim-3043) /share/uvmc-2.2//src/connect/sv/uvmc_tlm1.sv(652): Unresolved reference to 'm_get_if_mask'.
# Region: /uvmc_pkg::uvmc_tlm1_port_proxy::uvmc_tlm1_port_proxy__1
# ** Error: (vsim-3567) /share/uvmc-2.2//src/connect/sv/uvmc_tlm2.sv(412): No field named 'm_get_if_mask'.
# Region: /uvmc_pkg::uvmc_tlm2_port_proxy::uvmc_tlm2_port_proxy__1
# ** Error: (vsim-3567) /share/uvmc-2.2//src/connect/sv/uvmc_tlm2.sv(412): No field named 'm_get_if_mask'.
# Region: /uvmc_pkg::uvmc_tlm2_port_proxy::uvmc_tlm2_port_proxy__1
# ** Error: (vsim-3043) /share/uvmc-2.2//src/connect/sv/uvmc_tlm2.sv(412): Unresolved reference to 'm_get_if_mask'.
# Region: /uvmc_pkg::uvmc_tlm2_port_proxy::uvmc_tlm2_port_proxy__1
I have two connections in my desing, one TLM2 socket connection and one TLM1 analysis port connection.
The SystemVerilog transaction item (my_item) has the packing methods implemented in the class, on SystemC side (my_sc_item) I use converter specialization for conversion.
For example for the TLM2 connection, this is the code on SV side:
uvm_tlm_b_initiator_socket #(my_item) initiator;
initiator = new("initiator", this);
uvmc_tlm #(my_item)::connect(initiator, "uvmc_channel");
And on SC side:
tlm_utils::passthrough_target_socket<module, 32, my_sc_item> target;
uvmc::uvmc_connect(target, "uvmc_channel");
I used UVMconnect successfully before, thus I wonder what's wrong in this case.
Any idea where those errors comes from?
Thanks,
Thomas
Does
`uvm_do_with(REQ, CNST)
take into considiration the default constraints in the class defenition ?
From what I see it ignores those constaints.
If so is there a way to solve this ?
In the env, there is such uvm_config_db::set():
for (int i = 0; i < host_num; i++) begin
inst_name = $sformatf("*.v_seq.slv_seq[%0d]", i);
uvm_config_db#(uvm_event)::set(uvm_root::get(), inst_name, "evt", env.subenv[i].slv_agt.slv_mon.evt);
end
in the slv_seq, there is such uvm_config_db::get():
if(!uvm_config_db#(uvm_event)::get(null, this.get_full_name(), "evt", evt))
`uvm_fatal("NOEVT",{"evt must be set for: ",get_full_name(),".evt"});
When I use +UVM_CONFIG_DB_TRACE, I found such message:
UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1d/src/base/uvm_resource_db.svh(121) @ 2580000: reporter [CFGDB/GET] Configuration 'uvm_test_top.env.v_sqr.v_seq.slv_seq[k]evt' (type class uvm_pkg::uvm_event) read by = null (failed lookup)
If I uvm_config_db::set() in slv_mon like this:
uvm_config_db#(uvm_event)::set(uvm_root::get(), "*", "evt",evt);
there isn't such message, I think it configures successfully. there are multiple slv_mon and slv_seq instances, when there is only one valid slv_mon and slv_seq, the evt cann't pass successfully when it triggered. So I want to config evt of slv_mon to slv_seq using the bijective way. It isn't success at the moment, can anybody tell me the graceful way?
Thanks in advance
mrforever
What is best way to override default uvm severity types (UVM_INFO, UVM_ERROR, UVM_WARNING, UVM_FATAL) with custom report severity types. For example, instead of displaying :
UVM_INFO @ 0: reporter [RNTST] Running test test_read_modify_write...
UVM_INFO test_lib.sv(55) @ 0: uvm_test_top [test_read_modify_write] Printing the test topology :
I would like to display something like:
MY_INFO @ 0: reporter [RNTST] Running test test_read_modify_write...
MY_INFO test_lib.sv(55) @ 0: uvm_test_top [test_read_modify_write] Printing the test topology :
Hi,
Is it possible to configure multiple sequences in one phase for one sequencer? Like i have multiple sequencers in my env.
In one of the sequencer main pahse i am registering default sequnce as seq1. If in same test for same main phase if I register seq 2 as default sequnce what will happen?
- seq2 will be overridden by seq1 for main phase for that sequencer
or - it will add seq 2 in sequencer main phase queue to execute after seq1?
Thanks in advance for your time.
Thanks,
Akshay
When a driver returns a response to the sequence, it calls 'set_id_info()' to set the identifiers of the transactions returned. This way, the originating sequence can correlate the response and the originating transaction, by matching the 2 fields sequence_id and transaction_id.
This has a couple of drawbacks :
An improvement/fix to address these 2 issues would be to use field 'inst_id' (which is unique) instead of 'transaction_id' (user defined).
It looks to me the original intention was to use this field rather than 'transaction_id'.
The code change would be :
function void set_id_info(uvm_sequence_item item);
if (item == null) begin
uvm_report_fatal(get_full_name(), "set_id_info called with null parameter", UVM_NONE);
end
/* this.set_transaction_id(item.get_transaction_id()); */
this.set_transaction_id(item.get_inst_id());
this.set_sequence_id(item.get_sequence_id());
endfunction
In the Layered Sequencers,
As shown in the figure below, I want to use multiple lower layer sequencers(1,2,3) in parallel.
Is it possible?
If possible, Can you tell me how do I implement?
Sequencer(Upper) +-----> Sequencer(Lower1) ----> Driver
+-----> Sequencer(Lower2) ----> Driver
+-----> Sequencer(Lower3) ----> Driver
Hi,
I have created pre_reset and pre_configure phase in my test.
I have not registered any sequence for pre_reset and pre_configure phase but I have some delay in my pre_reset phase of the test.
Still i see both pre_reset and pre_configure phases starting at 0 time. why is it so?
Example below shows what I mean to say but it is not comple clean code.
class my test extends uvm_test;
// registration
virtual tast pre_reset (uvm_phase phase);
$display(in pre_rest phase);
#100;
top.rst = 0;
#100;
top.rst = 1;
endtask
virtual task pre_configure(uvm_phase phase);
$display(in pre_configure phase);
top.interrupt_en = 1;
endtask
here both messaged in pre_reset phase and in pre_configure phase are coming at 0 time only.
What I understood is pre_configure phase will be executed after pre_reset, reset and post_reset phase are over. so message in pre_configure should come after 200 timestamp only if I dont have anything for reset and post reset pahse.
Please correct me if I am wrong.
Hi, UVM Exports,
I am writing a test to put 2 uvm_env A and B together and hope to separate them in different domains. I hope to give each environment his own run_phases time line. how could I do this? thanks! hope you could provide some hints or several lines of code for my reference. thanks a lot!
In the uvm_reg_block::lock_model() , there is a check for duplicate names of the reg block. This check uses get_name(). Shouldn't it be using get_full_name() ??
the error that results is : `uvm_error("UVM/REG/DUPLROOT",
$sformatf("There are %0d root register models named \"%s\". The names of the root register models have to be unique",
n, get_name()))
-even when i have multiple instances of the uvm_reg_block in different heirarchies.