Hi there

A register can have different RTL implementation based on access_mode.

ie., When a register REG_1 is read in backdoor, actual HDLPATH of the register would point to 'top.abc.dout'.

When a register REG_1 is written in backdoor, actual HDLPATH of the register would point to 'top.abc.dout_temp'

We want to program different hdlpaths to REG_1 based on access mode (READ or WRITE).

Does UVM_REG provide ready-made hookups or methods like add_hdl_path_slice() methods to setup different hdlpaths to READ/WRITE backdoor access? (Inside the DPI based backdoor access itself?)

I checked that write_backdoor and read_backdoor methods need to be overwritten to setup different HDLPATHs based on READ/WRITE access modes. But this involves overriding string based DPI backdoor access factory methods. I'm looking for an alternative here, if it really exists.

Suggestions to this requirement, very much appreciated.

Best regards

Balasubramanian G

Hi all, i'm new both to this forum and to the verification (and electronic in general) world.

My problem is that i'm not carrying out a good tb for my design. More specifically my DUT is a FSM in which the concept of transaction is not well defined (i have a lot of signals through different interfaces and, basically, they must match clock by clock the desired values). In order to test the dut's outputs my idea was to replicate (without knowing the design code) the fsm in the scoreboard and so test dut's output againts scoreaboad's output. The problem arises here: when  and how i have to update my fsm? My previous approach was to have a set of monitors for the dut's input and a set of monitors for dut's output and, basically, the code of my scoreboard had this structure 

forever begin
   fifo_input_1.get(tr_input_1);
   fifo_input_2.get(tr_input_2);

   update_fsm(tr_input_1, tr_input_2);

   fifo_output_1.get(tr_output_1);
   fifo_output_2.get(tr_output_2);

   check_output(tr_output_1, tr_output2);
end

in which the fsm was updated every clock because each monitor produce a transaction at each clock.

Of cource this is a very bad approach, i suppose....

What is the best architecture choice to do what i have to do?

Thanks in advance!

I'm implementing our own version of uvm_report_server to format our log file format, and I noticed that simulation performance took a pretty big hit, and there is a fairly long delay at beginning of simulation before things start running. Is this normal when you overload default uvm_report_server? Are there practices that improve performance of uvm_report_server?

suppose my design is having fifos,counters and logic for some complex algorithm.

using uvm i can create agents to test signals in interfaces.

how to verify internal fifos using uvm environment?

do i need to verify seperately?

I'm having trouble using the config_db mechanism to set a property in a uvm component that is an object.

Using the same flow/mechanisms for an integer property seems to work fine but the setting of a property defined using uvm_field_object doesn't work.

The essence of the code is extracted below.

Any ideas?

Thanks.

Walker

  // my_foo_struct_t is class that extends foo_struct_t class
  my_foo_struct_t foo_struct;

  virtual function void build_phase(uvm_phase phase);

    super.build_phase(phase);

    chip = chip_t::type_id::create("c", this);

    foo_struct = new();

    // Set the foo_struct property in any sub-component to this component's foo_struct
    // foo_struct is a uvm_field_object in one component type
    // This doesn't work
    uvm_config_db#(foo_struct_t)::set(this, "*", "foo_struct", foo_struct);

    // Set the foo property in any sub-component
    // foo is a uvm_field_int in several component types
    // This does work
    uvm_config_db#(int)::set(this, "*", "foo", 33);

  endfunction : build_phase

 The UVM function uvm_hdl_force   format is 

My question is can I use a array path in the path?

For example :  uvm_hdl_force(  test_ben.cpu.block[0].instan[1].set[2] ,1 );

Can it work? Its compile is no problem.

Thank you very much~~

Hi UVM experts,

I am working on a testbench to verify register behavior and came a cross an issue with W0CRS register fields with reset value of 1.   Please correct me if i am wrong here.

A 3-bit register field of type W0CRS with default value 3'b101. W0CRS states "W: 1/0 no effect on/clears matching bit, R: sets all bits"

tx_byte_bus.configure(this, 3, 0, "W0CRS", 0, `UVM_REG_DATA_WIDTH'h00000005, 1, 1, 1);

and my testcase does the following transactions to verify the register:

after system reset and regModel.reset (reset all mirrored values to their default) -> write all 1's -> then followed by a read -> then followed by a 2nd read

I expected the first read return 3'b101 as W0CRS shouldn't change m_value after write-all-1's is done, but the test failed with an uvm_error complaining the mirrored value is 3'b000, not match DUT value 3'b101.

- if I update the default value to all 0's in both DUT and UVM_REG file, then test passed

- if I udpate the default value to all 1's in both DUT and UVM_REG file, then test failed with the same error.

Is this a bug with W0CRS register? 

thanks,

Judy

I'm seeing the uvm_object get_inst_id() function not returning unique, new IDs for new objects that I create.  More specifically, it's returning a repeating cycle of a few different IDs.  Looking under the hood at uvm_object.svh it's a pretty trivial mechanism so I can't see why it isn't working.  Also, in a derived class I created I mimicked the same mechanism and my mechanism works fine.

Test case and example output is below.  Note that the static instance count value seems to increment nicely as expected but the instance ID values seem to bear no relation to that count and repeat every 6 objects.

Am I missing something really obvious here or is this a possible bug.  I see this using UVM 1.1d downloaded from Accellera.

//////////////////////////////////////////////////////////////////////////////////////////////////////////////

class my_object_t extends uvm_object;

  static int next_id;

  int my_id;

  function new (string name="my_object");

    super.new(name);

    my_id = next_id++;

  endfunction : new

  `uvm_object_utils(my_object_t)

endclass

      begin

         my_object_t my_object;

         for (int i = 0; i < 100; i++)

           begin

              my_object = new();

              `uvm_info("", $sformatf("my object inst id is %d (0x%0x) or %0d, inst count is %d (0x%0x) or %0d", my_object.get_inst_id(), my_object.get_inst_id(), my_object.my_id,

                                      my_object.get_inst_count(), my_object.get_inst_count(), my_object.next_id), UVM_LOW)

           end

      end

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72135 (0x119c7) or 0, inst count is        9585 (0x2571) or 1

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72122 (0x119ba) or 1, inst count is        9586 (0x2572) or 2

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is         581 (0x245) or 2, inst count is        9587 (0x2573) or 3

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72126 (0x119be) or 3, inst count is        9588 (0x2574) or 4

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72120 (0x119b8) or 4, inst count is        9589 (0x2575) or 5

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       69783 (0x11097) or 5, inst count is        9590 (0x2576) or 6

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72135 (0x119c7) or 6, inst count is        9591 (0x2577) or 7

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72122 (0x119ba) or 7, inst count is        9592 (0x2578) or 8

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is         581 (0x245) or 8, inst count is        9593 (0x2579) or 9

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72126 (0x119be) or 9, inst count is        9594 (0x257a) or 10

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72120 (0x119b8) or 10, inst count is        9595 (0x257b) or 11

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       69783 (0x11097) or 11, inst count is        9596 (0x257c) or 12

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72135 (0x119c7) or 12, inst count is        9597 (0x257d) or 13

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72122 (0x119ba) or 13, inst count is        9598 (0x257e) or 14

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is         581 (0x245) or 14, inst count is        9599 (0x257f) or 15

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72126 (0x119be) or 15, inst count is        9600 (0x2580) or 16

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72120 (0x119b8) or 16, inst count is        9601 (0x2581) or 17

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       69783 (0x11097) or 17, inst count is        9602 (0x2582) or 18

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72135 (0x119c7) or 18, inst count is        9603 (0x2583) or 19

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72122 (0x119ba) or 19, inst count is        9604 (0x2584) or 20

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is         581 (0x245) or 20, inst count is        9605 (0x2585) or 21

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72126 (0x119be) or 21, inst count is        9606 (0x2586) or 22

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72120 (0x119b8) or 22, inst count is        9607 (0x2587) or 23

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       69783 (0x11097) or 23, inst count is        9608 (0x2588) or 24

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72135 (0x119c7) or 24, inst count is        9609 (0x2589) or 25

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72122 (0x119ba) or 25, inst count is        9610 (0x258a) or 26

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is         581 (0x245) or 26, inst count is        9611 (0x258b) or 27

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72126 (0x119be) or 27, inst count is        9612 (0x258c) or 28

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72120 (0x119b8) or 28, inst count is        9613 (0x258d) or 29

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       69783 (0x11097) or 29, inst count is        9614 (0x258e) or 30

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72135 (0x119c7) or 30, inst count is        9615 (0x258f) or 31

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72122 (0x119ba) or 31, inst count is        9616 (0x2590) or 32

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is         581 (0x245) or 32, inst count is        9617 (0x2591) or 33

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72126 (0x119be) or 33, inst count is        9618 (0x2592) or 34

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72120 (0x119b8) or 34, inst count is        9619 (0x2593) or 35

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       69783 (0x11097) or 35, inst count is        9620 (0x2594) or 36

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72135 (0x119c7) or 36, inst count is        9621 (0x2595) or 37

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is       72122 (0x119ba) or 37, inst count is        9622 (0x2596) or 38

UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is         581 (0x245) or 38, inst count is        9623 (0x2597) or 39

This is somewhat old but I wish I could find better ways. I need a scoreboard class that takes in 2 types of transaction via uvm_analysis_imp, and currently the only way of doing it is using `*_decl macro. I'm hoping there is a better way since I'm not sure about the impact of using such macro on other classes. If I understand the class reference correctly, using _decl macro essentially creates a different set of uvm base classes, so if I have 2 scoreboards, both using the same _decl macro with same suffix would there be a conflict? for example:

file:scoreboard1.svh

`uvm_analysis_imp_decl(_rd)

class scoreboard1 extends uvm_scoreboard;

  uvm_analysis_imp_rd #(T1,scoreboard1) imp1;

  uvm_analysis_imp #(T2,scoreboard1) imp2;

  function void write_rd(T1 t); //Have to add _rd due to imp_decl macro

  endfunction

  function void write(T2 t); //Default method

endclass

-end of file-

file:scoreboard2.svh

`uvm_analysis_imp_decl(_rd)

class scoreboard2 extends uvm_scoreboard;

  uvm_analysis_imp #(T1,scoreboard1) imp1;

  uvm_analysis_imp_rd #(T2,scoreboard1) imp2;

  function void write(T1 t); //Method for T1

  endfunction

  function void write_rd(T2 t); //Method for T2

endclass

-end of file-

Would this create a conflict at compile time? What is best practice for implementing multiple analysis_imp in a single class?

Hello All,

New here. I am wondering if there is a way to make uvm_reg_block to dump the current values of all the registers in that block to a log file? If not a built-in method, then does anybody have a snippet I could borrow.

Thank you!

Hi,

I'm trying to perform backdoor access to uvm_mem.

For some reason, the Xcheck_accessX function in uvm_mem, override my map with pseudo map.

From this function:

        rw.map = uvm_reg_map::backdoor();

From uvm_reg_map:

in can controller we have many sub modules like

acceptance filter

registers

frame generators

synchronizers etc...

how to create verification env for it.

do i need to verify all these sub components using uvm env only or seperately.

each can controller acts as master and slave, if i have 4 can nodes, how many agents are required and does each node have both master and slave capabilities.

Is min_size or max_size ever checked after elaboration to check port/imp connections? I grepped through the 1.1d code and didn't see anything. The min_size and max_size are both set to 1 for an analysis_imp, however if you don't connect an analysis_port to an imp or if you connect more than 1 then there are no errors. This seems like a pretty critical oversight since it will allow imps to be unconnected regardless of the setting of min_size and max_size. Since this is a pretty easy error to make then it makes debug unnecessarily difficult.

I did confirm that the uvm_analysis_imp::get_provided_to works as expected. I would expect this number to be checked after all connections are complete and compared to min_size and max_size and error to be reported if out not the correct value.

Rlated to this, why are the constructors for the imp classes not overridden so as to allow different values for min_size and max_size. Right now they are hardcoded to 1 with now way to change them. I can conceive of cases where you might allow multiple analysis ports to write to an imp.

Hello,

I have two classes in two different files:

class B : public uvm_component

{

...

do_something();

...

}

class A : public uvm_component

{

....

SetCallback(boost::bind(&B::do_something, *pB, _1, _2));

...

}

When I try to compile this, I have this error:

"/home/cadence/UVM_ML-1.3.4.3/ml/frameworks/uvm/sc/base/uvm_component.h", line 60: error:
          "sc_core::sc_module::sc_module(const sc_core::sc_module &)"
          (declared at line 398 of
          "$CDSROOT/tools/systemc/include_pch/64bi
          t/sysc/kernel/sc_module.h") is inaccessible
  class uvm_component : public sc_core::sc_module, public uvm_typed {
                               ^
          detected during:
            implicit generation of "uvm::uvm_component::uvm_component(const
                      uvm::uvm_component &)" at line 14 of
            implicit generation of "collector::collector(const collector &)"
                      at line 14 of

Any idea?

Thanks

 

hi,

  In   uvm_phase file  of uvm1.2,  I understand that  before_phase.m_successors.delete(after_phase)  which is  the  978th line code of  add method should be   'before_phase.m_predecessors.delete(after_phase) ' , that is right ?

 965   // IN BETWEEN 'BEFORE' and 'AFTER' PHASES
 966   else if (before_phase != null && after_phase != null) begin
 967     if (!after_phase.is_before(before_phase)) begin
 968       `uvm_fatal("PH_ADD_PHASE",{"Phase '",before_phase.get_name(),
 969                  "' is not before phase '",after_phase.get_name(),"'"})
 970     end
 971     // before and after? add 1 pred and 1 succ
 972     begin_node.m_predecessors[after_phase] = 1;
 973     end_node.m_successors[before_phase] = 1;
 974     after_phase.m_successors[begin_node] = 1;
 975     before_phase.m_predecessors[end_node] = 1;
 976     if (after_phase.m_successors.exists(before_phase)) begin
 977       after_phase.m_successors.delete(before_phase);
 978       before_phase.m_successors.delete(after_phase);
 979     end
 980   end // if (before_phase != null && after_phase != null)  

Say I have these sequences:

class cfg_seq extends uvm_sequence #(obj_type1);
  `uvm_object_utils(cfg_seq)
  rand int unsigned size_x;
  rand int unsigned size_y;
...
  task body;
    //Generate objects based on size_x and size_y
  endtask
endclass

class item_seq extends uvm_sequence #(obj_type2);
  `uvm_object_utils(cfg_seq)
  rand int unsigned size_x;
  rand int unsigned size_y;
...
  task body;
    //Generate objects based on size_x and size_y
  endtask
endclass

I want to use them in a virtual sequence like this:

class test_vseq extends uvm_sequence;
  `uvm_declare_p_sequencer(some_vseqr)
  `uvm_object_utils(test_vseq)

  rand int unsigned size_x;
  rand int unsigned size_y;

  rand cfg_seq cfg;
  rand item_seq item;

  //This is what I'm trying to achieve
  constraint size_c {
    cfg.size_x == this.size_x;
    cfg.size_y == this.size_y;
    item.size_x == this.size_x;
    item.size_y == this.size_y;
  }
...
  task body;
    `uvm_do_on(cfg, p_sequencer.cfg_seqr)
    `uvm_do_on(item, p_sequencer.item_seqr)
  endtask
endclass

What I'm trying to do is that I set "size_x" and "size_y" in test_vseq and have cfg and item pick it up from test_vseq, so I don't have to set them separately in config_db. What's the best way to do this?

Hi, all

     When i read the uvm source code, I had a puzzle as follow:

     Why are the twelve runtime phases added into m_uvm_schedule phase instead of being added directly m_uvm_domain domain in file uvm_domain.svh?

  static function void add_uvm_phases(uvm_phase schedule);

    schedule.add(uvm_pre_reset_phase::get());
    schedule.add(uvm_reset_phase::get());
    schedule.add(uvm_post_reset_phase::get());
    schedule.add(uvm_pre_configure_phase::get());
    schedule.add(uvm_configure_phase::get());
    schedule.add(uvm_post_configure_phase::get());
    schedule.add(uvm_pre_main_phase::get());
    schedule.add(uvm_main_phase::get());
    schedule.add(uvm_post_main_phase::get());
    schedule.add(uvm_pre_shutdown_phase::get());
    schedule.add(uvm_shutdown_phase::get());
    schedule.add(uvm_post_shutdown_phase::get());

  endfunction

  static function uvm_domain get_uvm_domain();
 
    if (m_uvm_domain == null) begin
      m_uvm_domain = new("uvm");
      m_uvm_schedule = new("uvm_sched", UVM_PHASE_SCHEDULE);
      add_uvm_phases(m_uvm_schedule);
      m_uvm_domain.add(m_uvm_schedule);
    end
    return m_uvm_domain;
  endfunction

Could the two functions be mergered one function as follow?

  static function uvm_domain get_uvm_domain();
 
    if (m_uvm_domain == null) begin
      m_uvm_domain = new("uvm");
      m_uvm_domain.add(uvm_pre_reset_phase::get());
      m_uvm_domain.add(uvm_reset_phase::get());
      m_uvm_domain.add(uvm_post_reset_phase::get());
      m_uvm_domain.add(uvm_pre_configure_phase::get());
      m_uvm_domain.add(uvm_configure_phase::get());
      m_uvm_domain.add(uvm_post_configure_phase::get());
      m_uvm_domain.add(uvm_pre_main_phase::get());
      m_uvm_domain.add(uvm_main_phase::get());
      m_uvm_domain.add(uvm_post_main_phase::get());
      m_uvm_domain.add(uvm_pre_shutdown_phase::get());
      m_uvm_domain.add(uvm_shutdown_phase::get());
      m_uvm_domain.add(uvm_post_shutdown_phase::get());
    end
    return m_uvm_domain;
  endfunction