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How to change the print format used by UVM?

December 18, 2013, 7:18 am
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I need to dump the contents of a queue in my scoreboard. When the queue is large and the items in the queue have a lot of properties, the report becomes very large and hard to parse. This is because the default UVM print format is table.

    foreach(my_q[i]) begin
      `uvm_info("REPORT", $sformatf("my_q[%0d]:\n%s",
        i, my_q[i].sprint()), UVM_LOW)
    end

I'm interested in printing each item on a single line. How do I accomplish the following:

  1. Change the format from the command line?
  2. Change the default format that is used by my whole scoreboard?
  3. Change the format that is used only by the method that is dumping the queue contents?

You can edit and re-run the simple example of this issue here: http://www.edaplayground.com/s/4/656

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How to verify reset processing with UVM?

December 19, 2013, 12:46 am
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Hello everybody.

 

How to verify RTL's reset processing? It seems, there are no examples to demonstrate it.

My RTL design is optimized with synchronuous reset, but resest signal do not feed all registers (for example no need to reset shiftregs in many cases, but resettig FSM is a must). I have already found some bugs in reset processing, but I want to do it with UVM. What is a way to do it?

One more agent, including driver & monitor for reset? One more seq_item for it?

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a question about the compiling order

December 20, 2013, 5:29 am
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Hi, all

 

      I fond the function uvm_report_error is called in uvm_object.svh when I read the UVM-1.1d source code, but the file uvm_object.svh is compiled before the file uvm_globals.svh in the file base.svh. Would you please tell me what is wrong with it?

 

      Thanks a lot in advanced!

 

Best Regards

 

QIN

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demoting UVM_ERROR

December 24, 2013, 1:35 am
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I'm trying to cancel an error,

in test.build_phase :

set_report_severity_id_action_hier(UVM_ERROR, "PKT_ERR", UVM_NO_ACTION);

but the error doesn't go away

 

EDIT:

 

problem solved: in test connect_phase if full hier given it works :

 

env.href.set_report_id_action_hier(UVM_ERROR, ""PKT_ERR", UVM_NO_ACTION);

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uvm_resource_db/uvm_config_db usage

December 24, 2013, 3:06 am
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UVM agents use uvm_resource_db/uvm_config_db to configure components. what is the difference between these two?..

how does the below code work,

 

uvm_resource_db # (virtual bus_if.monitor)::read_by_name("interfaces", bus_if_monitor", m_env.m_bus_mon.mi)

 

uvm_config_db#(int)::set(this, "env.*","m_reg_state", venv::START)

 

 

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Why is the m_uvm_schedule inserted between m_uvm_domain and the12 realtime phases?

December 26, 2013, 9:47 pm
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Hi, all

 

        Why is not the 12 realtime phases directly wrapped by m_uvm_domain but also the m_uvm_schedule is inserted between m_uvm_domain and the 12 realtime phases?

 

     Thank you in advanced!

 

BR

 

QIN

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How to call uvm_error from a static method?

January 2, 2014, 2:01 pm
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What is the recommended way to call UVM report functions and macros from a static method in a uvm_component?

 

Having the following code:

  static function static_check();
    `uvm_error("ID", "Something failed");
  endfunction

causes a compile error:

** Error: testbench.sv(15): (vlog-2888) Illegal to access non-static method 'uvm_report_enabled' from a static method.

Full example can be edited and run here: http://www.edaplayground.com/s/4/762

 

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Accessing an Output port through Backdoor using UVM Register Model

January 4, 2014, 1:27 am
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Hi Guys,

  I am using UVM Register model to mimmick RTL's register implementation. Some registers are not implemented in RTL which are going to be connected to output port of some other module.

I have got a HDL path of register as an output port declaration of some module.

 

Something like:

   The HDL path is: "tb_top.dut_u.interrupt_module_u.o_ext_interrupt"

 

o_ext_interrupt is declared as output port inside interrupt_module, which is not connected to any other wire or register.

 

Can this output port's value be changed by writing to it via UVM BACKDOOR ? 

 

I am using following API:

register_name.write(status,data,UVM_BACKDOOR,default_map);

 

I dont see any change in value in the register. I think it is happening because the destination (o_ext_interrupt) is output of the module.

 

I am using Cadence's simulator: irun.

 

Please help if anyone is aware of such issue.

 

Regards,

Vismay.

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Controlling sequence library distibution

January 5, 2014, 10:01 am
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Hi All, 

 

I have a question about controlling sequence library distibution. I would like to give the test writer the ability to control sequences distribution. For that i am  using the uvm_sequence_library class. I saw that the index of a sequence in the library is determined by the order of sequence registration to the library (using `uvm_add_to_seq_lib macro). but this raises problem when removing sequences for example:

 

Project1 :

 

Sequence lib code:

constratint select_sequence_c { select_rand dist {   0:=20, // sequence_A

1:=100, // sequence_B

2:=20  // sequence_C

};}

 

The test owner would like to override the default distribution so in the test there is the following constraint layering:

constratint select_diff_dist { select_rand dist {  /*0:=20, // sequence_A*/

1:=30, // sequence_B

2:=30  // sequence_C

};}

 

Next project . Project2 does not include sequence A anymore so it was removed from the sequence library . Sequence index is now shifted.

 

constratint select_sequence_c { select_rand dist {  

0:=100, // sequence_B

1:=20  // sequence_C

};}

 

Now the test should be changed since index 1 does not point to sequence B anymore ( and so on…):

constratint select_diff_dist { select_rand dist {

1:=30, // sequence_B

2:=30  // sequence_C

};}

 

In OVM we used string based hash which is now deprecated:

constraint select_seq seq_kind dist {seq_kind dist Get_seq_kind(“sequence_A”) :=20,

seq_kind dist Get_seq_kind(“sequence_B”) :=20,

seq_kind dist Get_seq_kind(“sequence_C”) :=20};

}

 

 

Any idea how to solve this?

 

Thanks, 

Ilan

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the bug of the sync of run_phase and post_shutdown_phase!

January 6, 2014, 11:09 pm
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Hi, all

 

 We have one monitor and one driver as follow:

 

class monitor extends uvm_monitor;

 `uvm_component_utils(monitor)

   function new(string name, uvm_component parent);
      super.new(name, parent);
   endfunction

   virtual task post_shutdown_phase(uvm_phase phase);
   
     #50ns;
     `uvm_info(get_type_name(), "Monitor is printing at post_shutdown_phase executing...", UVM_LOW )
   
   endtask: post_shutdown_phase
   
   virtual function void phase_ready_to_end(uvm_phase phase);
     if(phase.get_name == "post_shutdown")
       `uvm_info(get_type_name(), "Monitor is printing at phase_ready_to_end...", UVM_LOW )
   
   endfunction: phase_ready_to_end
   
   
   virtual function void phase_ended(uvm_phase phase);
     if(phase.get_name == "post_shutdown")
       `uvm_info(get_type_name(), "Monitor is printing at phase_ended...", UVM_LOW )
   
   endfunction: phase_ended

endclass : monitor

 

 

 

class driver extends uvm_driver;

  `uvm_component_utils(driver)

  function new(string name, uvm_component parent);
    super.new(name);
  endfunction

  task run_phase(uvm_phase phase);
    phase.raise_objection(this, "Starting test");
    #100ns;
    `uvm_info(get_type_name(), "Driver is printing at run_phase executing...", UVM_LOW )    
    phase.drop_objection(this, "Finishing test");
  endtask: run_phase

  virtual function void phase_ready_to_end(uvm_phase phase);
    if(phase.get_name == "run")
      `uvm_info(get_type_name(), "Driver is printing at phase_ready_to_end...", UVM_LOW )

  endfunction: phase_ready_to_end

  virtual function void phase_ended(uvm_phase phase);
    if(phase.get_name == "run")
      `uvm_info(get_type_name(), "Driver is printing at phase_ended...", UVM_LOW )

  endfunction: phase_ended

endclass: driver

 

 when it run one of cases, it printed the information as follow:

 

# UVM_INFO @ 0: reporter [RNTST] Running test tc_read_ver_reg...
# UVM_INFO ../../monitor.sv(41) @ 0: uvm_test_top.tb.agent.monitor [monitor] Monitor is printing at phase_ready_to_end...
# UVM_INFO ../../monitor.sv(35) @ 50000: uvm_test_top.tb.agent.monitor [monitor] Monitor is printing at post_shutdown_phase executing...
# UVM_INFO ../../driver.sv(22) @ 100000: uvm_test_top.tb.agent.driver [driver] Driver is printing at run_phase executing...
# UVM_INFO ../../driver.sv(28) @ 100000: uvm_test_top.tb.agent.driver [driver] Driver is printing at phase_ready_to_end...
# UVM_INFO ../../monitor.sv(48) @ 100000: uvm_test_top.tb.agent.monitor [monitor] Monitor is printing at phase_ended...
# UVM_INFO ../../driver.sv(34) @ 100000: uvm_test_top.tb.agent.driver [driver] Driver is printing at phase_ended...
#

 

The post_shutdown_phase of the monitor reached to phase_ready_to_end at 0, but it's task post_shutdown_phase did not finish until  @ 50000.

 

What is wrong with it?

 

Thank you in advanced!

 

BR

 

QIN

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the worthless code in the file uvm_callback.sv?

January 16, 2014, 7:21 pm
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Hi, all

 

    There is  a piece of code in the function m_add_tw_cbs of the uvm_typed_callbacks#(type T=uvm_object) of the file uvm_callback.sv as follow:

 

        if(m_t_inst.m_pool.first(obj)) begin
      do begin
        if($cast(me,obj)) begin
          q = m_t_inst.m_pool.get(obj);
          if(q==null) begin
            q=new;
            m_t_inst.m_pool.add(obj,q);
          end
          if(m_cb_find(q,cb) == -1) begin
            if(ordering == UVM_APPEND)
              q.push_back(cb);
            else
              q.push_front(cb);
          end
        end
      end while(m_t_inst.m_pool.next(obj));
    end

 

  

   I want to know whether the red piece is worthless ?

 

 

   Thank you in advanced!

 

 

BR

 

QIN

 

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What's the matter with $cast()?

January 22, 2014, 12:02 am
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Hi, all

 

 

     I has an example as follow:

 

 

class BasePacket;
  int A = 1;
  int C = 2;
 
  function void printA;
    $display("BasePacket::A is %d", A);
  endfunction : printA
 
  virtual function void printC;
    $display("BasePacket::C is %d", C);
  endfunction : printC
endclass : BasePacket


class My_Packet extends BasePacket;
  int A = 3;
  int C = 4;
 
  function void printA;
    $display("My_Packet::A is %d", A);
  endfunction: printA
 
  virtual function void printC;
    $display("My_Packet::C is %d", C);
  endfunction : printC
endclass : My_Packet

BasePacket   P1 = new;
My_Packet     P2 = new;

 

 

Case one:

initial begin
//P1 = P2;
P1.printA;
P1.printC;
$cast(P2, P1);
P2.printA;
P2.printC;
end

 

...
# BasePacket::A is           1
# BasePacket::C is           2
# ** Error: (vsim-3971) $cast to type 'class work.obc_pkg_sv_unit::My_Packet' from 'class work.obc_pkg_sv_unit::BasePacket' failed in file ../../sv/top/bip4_vtop.sv at line 80.
#    Time: 0 ps  Iteration: 0  Instance: /bip4_vtop
# My_Packet::A is           3
# My_Packet::C is           4
...

 

 

Case Two:
initial begin
P1 = P2;
P1.printA;
P1.printC;
$cast(P2, P1);
P2.printA;
P2.printC;
end

...
# BasePacket::A is           1
# My_Packet::C is           4
# My_Packet::A is           3
# My_Packet::C is           4

...

 

 

Case one, I didn't assign P1 with P2, the simulator reported error information as above;

the type of P1 is not a superclass of the P2 type?

 

Case twon, I assign P1 with P2 at the begbining, the simulator reported normally as above;

 

Why the assignment of P2 with P1 is cast-compatible after assigned P1 with P2? 

How to do the simulator judge the cast-compatible?

 

So I want to know what the assignment of P1 with P2 does?

 

Thank you in advanced.

 

BR

 

QIN

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new to UVM forum

January 23, 2014, 10:48 pm
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Hi, 

I am new to UVM forum. Just testing that account/post works. 

Please ignore this thread. 

 

Thanks

Vic

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Randomization in Configuration Classes

January 26, 2014, 7:10 pm
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Why the one need to set rand variables in configuration classes ,,, 

 

my knowledge is that Virtual Sequencer is the only component whose responsibility to generate random variables, isn't it ?

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Compilation error in IUS9.2-S023

February 5, 2014, 5:50 am
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Hello,

 

    I am trying to simulate i2c top file which contains a sequence in which i have raised objection and dropped objection in the body of the sequence as follows: I am facing compilation issues such as "starting_phase" is undeclared identifier whereas the code compiles fine with questasim. Is IUS version 9.2_s023 compatible with uvm-1.1a? Is there any additional switch required to run ?

 

Command given : irun -uvm i2c_top.sv

 

Code Snippet

---------------------

i2c_top.sv

========

`include "uvm_pkg.sv"

 import uvm_pkg::* ;

 `include "uvm_macros.svh"

 `include i2c_txn.sv

 `include i2c_interface.sv

  `include i2c_sequence.sv

 

i2c_sequence.sv

=============

task body()

if(starting_phase!=null)

  starting_phase.raise_objection(this);

 

    repeat(1)

      begin

        req=i2c_txn::type_id::create(req);

       start_item(req)

       finish_item(req)

     end

 

if(starting_phase!=null)

   starting_phase.drop_objection(this)

 

Error snippet

--------------------

i2c_top.sv
      if(starting_phase!=null)
                      |
ncvlog: *E,UNDIDN (i2c_slave_sequence.sv,10|22): 'starting_phase': undeclared identifier [12.5(IEEE)].
      if(starting_phase!=null)
                      |

ncvlog: *E,UNDIDN (i2c_slave_sequence.sv,54|22): 'starting_phase': undeclared identifier [12.5(IEEE)].
  uvm_config_db#(virtual i2c_if)::set(uvm_root::get(), "*", "i2c_vif", intf);
              |
ncvlog: *E,NOPBIND (i2c_top.sv,40|14): Package uvm_config_db could not be bound.
        module worklib.i2c_top:sv
                errors: 1, warnings: 0
        Total errors/warnings found outside modules and primitives:
                errors: 4, warnings: 0

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problem about parameterized test and factory mechanism

February 6, 2014, 10:10 pm
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Hi, all

 

I want to use the factory mechanism to write one reusable test, this is the codes

class my_test #(parameter TSID=0) extends uvm_test;
  typedef my_test #(TSID) this_typ;

  typedef uvm_component_registry #(my_test #(TSID), $sformatf("my_test%0d", TSID)) type_id;

  static function type_id get_type();
    return type_id::get();
  endfunction : get_type

  function new(string name = "my_test", uvm_component parent=null);
    super.new(name,parent);
  endfunction : new
  ...
endclass

But I met such a compile error:

 

Error-[NCE] Non-constant expression
  The following expression should be a constant.
  Expression: $sformatf("my_test%0d", TSID)
  Source info:   typedef uvm_component_registry #(my_test #(TSID), 
  $sformatf("my_test%0d", TSID)) type_id;
...
 
If the second parameter should be a constant or constant expression in  
  typedef uvm_component_registry #(my_test #(TSID), $sformatf("my_test%0d", TSID)) type_id;

then how can i distinguish the specialized test using TSID which is from run option (my original idea is that using parameter TSID to distinguish the different specialized test)?

 

Second problem, my_test is a generic class now, where should the specialized test define and how to define if my original idea is feasible?

 

Regards

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Status UVM_HAS_X is not reported when register value is X

February 14, 2014, 4:24 pm
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In uvm_reg_map::do_bus_read() task, after the call to adapter.bus2reg() function, do_bus_read() function checks for any Xs in data field.

 

Code from uvm_reg_map:

 

      uvm_reg_bus_op rw_access;
      uvm_reg_data_logic_t data;
 
      data = rw_access.data & ((1<<bus_width*8)-1);
 
      rw.status = rw_access.status;
 
      if (rw.status == UVM_IS_OK && (^data) === 1'bx)
        rw.status = UVM_HAS_X;
 
Here, rw_access.data is of type "bit" and is assigned to data which is of type "logic". and then data is checked for Xs. But, as rw_access.data is "bit" type, it will never contain Xs or Zs.
As a result, data will never have Xs, so rw.status will not set to UVM_HAS_X. So even if bus2reg function samples Xs from the bus, those Xs never make upto tasks in uvm_reg_map class.
 
Some supporting code::
uvm_reg_defines.svh: `define UVM_REG_DATA_TYPE bit
uvm_reg_model.svh  :  typedef `UVM_REG_DATA_TYPE unsigned [`UVM_REG_DATA_WIDTH-1:0]  uvm_reg_data_t ;
uvm_reg_item.svh: 
typedef struct {
  uvm_access_e kind;
  uvm_reg_addr_t addr;
  uvm_reg_data_t data;
  int n_bits;
  uvm_reg_byte_en_t byte_en;
  uvm_status_e status;
} uvm_reg_bus_op;

 

 
In my testbench, I want uvm_reg_map to set the status to UVM_HAS_X whenever data received for a register read transaction from DUT is X. How do I achieve that?
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Implementing 8b10b Encoding/Decoding in UVM UVC

February 17, 2014, 4:43 am
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Hello everyone,

 

I need to implement 8b10b encoding and decoding functions in a serial UVC I am developing. However, I am unsure of the best method to use to apply the 8b10b coding algorithm. My first thought was to create a set of 8b10b encoding/decoding tables using a struct, pass the generated bytes/characters into the tables, and continue using the resulting value in the transactions. However, this doesn't seem to be the most efficient method to use.

 

Has anyone ever done this before, and if so, can you give me a few pointers to get me started in the right direction? Thanks!

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We named our new dog UVM

February 28, 2014, 9:29 am
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UVM doesn't have to be serious all the time, does it?

 

fyi... we got a new dog to keep us company in the office. His name is uvm. He's a good dog. He does tricks, but he can't jump.

 

www.realityreused.com/support.html

 

-neil

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XML output and SQL databases for debug

March 2, 2014, 7:03 pm
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Debug is extremely difficult to do in large, constrained-random simulations.

1) Even if there is large amounts of data available (such as UVM seq-item dumps), it is extremely slow to analyze the standard text outputs, and requires lots of script writing for each new bug

2) There are times when multiple streams of different sequence-items must be parsed in order to put the suspect sequence-item into context.

 

I would like to propose adding another UVM output format: XML

 

Then standard XML report-writers could be used to analyze the multiple output streams and generate statistics or identify possible failures or the failures themselves.

 

I would then to also like to propose loading that data into SQL databases for more complicated analysis and creation of standard reports.

 

Erik Jessen

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