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IP-XACT vendor extensions to support UVM seq-items

March 2, 2014, 7:15 pm
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IP-XACT has a standard method for capturing register information.  Including coping with having one field determine how to parse other fields in other registers.

 

UVM seq-items have `uvm_fields, but these have some problems, including:

1) in large seq-items, hitting maximum macro length in chars - this requires removing fields or options or whitespace.

2) It appears that the `uvm fields consume runtime every time an object is created.

3) no way to go from human-readable documentation to a list of registers with clear pack/unpack.

 

I would like to propose vendor extensions in IP-XACT for UVM seq-items, so that:

1) human-readable documentation can be generated.

2) source-code can be generated for packing/unpacking seq-items (C, SV, SV+UVM, Python, and lab-debug tools)

3) functional-coverage requirements could be captured in IP-XACT and functional-coverage code could be generated

4) requirements could be captured and then output could be generated into formats suitable for

    a) Formal verification

    B) simulation-based assertions

    c) post-processing and analyzing data collected in the lab.

5) UVM agents/monitors could be generated.

 

Given that this is a 'green-fields' situation there is no reason why IP-XACT vendor extensions could not fully support all concepts in UVM in a user-friendly manner.

This would also close a gap in IP-XACT, so that it is easier for IP-vendors to completely document how they generate (or expect) traffic, so users can verify pre-purchase if the IPs are compatible.

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Why is UVM_REG faster than RGM

March 11, 2014, 8:16 pm
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Why is UVM_REG faster than RGM ?

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Question about uvm_config_db of SV interface

March 21, 2014, 3:08 pm
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Hi,

 

I have a question when I use uvm_config_db for interface connection.

 

Generally, I know we use set() and get() function of "uvm_config_db" when we connect interface instance with virtual interface.

 

As I know, uvm_config_db#(virtual aaa_intf)::set() is described inside top testbench module.

And uvm_config_db#(virtual aaa_intf)::get() is some phase of inside class.

 

What I want to do is to move set() function into some phase of class.

Is it possible?

 

If possible, which phase can I use not to be no problem in topology?

Could you give me an example?

I generally descirbes uvm_config_db#(virtual aaa_intf)::get() in connect_phase.

 

 

Thanks & Regards,

YYN

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UVM Virtual Registers (UVM_VREG) examples?

March 27, 2014, 8:54 am
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Are there any good examples/post out there for UVM Virtual Registers (UVM_VREG) implementation?  I am currently evaluating and having issues with read/write to some the uvm_vreg_field's.

 

Thanks in advance.

 

 

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run_test

April 9, 2014, 2:04 pm
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Passing sequence_items from v-sequence to sub-sequence?

April 10, 2014, 3:13 pm
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Is there a way for a virtual sequence to pass a sequence_item (that it has already created) to a sub-sequence, say for instance to an agent sequence, without using a TLM?

 

I really would like to avoid adding a TLM to the agents sequencer if I can avoid it.

The sub-sequence would be invoked from the v-sequence by calling start().

The sequence_item is a potentially largish data structure so using the `uvm_do_on_with macro is a bit unwieldy.

 

I think I see a sneeky way to do it by using the parents mid_do() method, but haven't tried it yet and wondering if there's a more direct way I'm not seeing.

 

Thanks in advance. ;)

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Regarding multiple reset test

April 13, 2014, 11:10 pm
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Hi,

 

I am implementing multiple reset inside UVC componenets (sequencer, driver, monitor and etc).

 

When reset is asserted between get_next_item() and item_done(), the following error is issued.

 

UVM_ERROR (SEQREQZMB) The task responsible for requesting a wait_for_grant on sequencer '....' for sequence '...' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues.

 

 

I guess this error is caused that queue for sequence item already gets a item to transfer into driver.

 

How can I fix this problem?

How can I remove current item from the arbitration queue?

 

My UVC is using run_phase(). I don't use main_phase().

So, I would like to control it using run_phse().

 

Thanks & Regards,

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uvm_vreg increment issues

April 14, 2014, 10:56 am
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I am working an a block that requires two different type of buffer descriptors, let call them bd_base, bd_ext.

bd_base is size 8 bytes and bd_ext is size 32 bytes.  These are implemented on a 64 bit (8 byte) bus/memory.

For now I set the memory size to be 'd100000 with datasize 64bits.

 

I have ran a simulation with bd_base which vreg size is equal to the bus width and the increment to the next vreg[i+1] is correct.

 

However, when running with bd_ext with vreg size=32 bytes (4x the size of the bus), the increment to the next vreg[i+1] is off.  The offset for a particular example for each vreg is computed as:

 

 

BD[0] address=0x1118e0
BD[1] address=0x111960
BD[2] address=0x1119e0
BD[3] address=0x111a60
BD[4] address=0x111ae0
BD[5] address=0x111b60
BD[6] address=0x111be0

128-byte offset

 

I would expect

 

BD[0] address=0x1118e0
BD[1] address=0x111900
BD[2] address=0x111920
BD[3] address=0x111940
BD[4] address=0x111960
BD[5] address=0x111980
BD[6] address=0x1119a0

32-byte offset

 

Perhaps I am on the wrong trail, but I have narrowed down the issue to the following lines of code:

 

uvm_mem.svh (line 1328 - get_addresses function)

 

     addr[i] = addr[i] + map_info.mem_range.stride * offset;

 

uvm_reg_map.svh (line 890 - m_set_mem_offset function)

 

     stride = (max2 - max)/(mem.get_size()-1);

 

uvm_vreg.svh (lines 995-996 - allocate)

 

      int min_incr = (this.get_n_bytes()-1) / mem.get_n_bytes() + 1;
      if (incr == 0) incr = min_incr;

 

uvm_vreg.svh (lines 1073 - get_offset_in_memory function)

 

      return this.offset + idx * this.incr;

 

uvm_vreg.svh (lines 1353 - read task)

 

   addr = this.offset + (idx * this.incr);

 

From what I can see the uvm_mem stride variable already determines the correct offset and the incr variable is not needed to compute the next address/offset in the read or get_offset_in_memory function.  As a hack, I removed the (* this.incr - in red) in both and the simulation behaves as I expect.

 

 

 

 

Just some more info if needed:

 

1. I am currently using UVM package 1.1d

 

2. I am using define UVM_REG_DATA_WIDTH=64 for bd_base and UVM_REG_DATA_WIDTH=256 for bd_ext

 

3. Register bd_ext class:

 

class ral_vreg_enet_bd extends uvm_vreg;
    rand uvm_vreg_field READY;

...

   function new(string name = "ral_vreg_enet_bd", int unsigned n_bits = 256);
     super.new(name, n_bits);
      this.READY = uvm_vreg_field::type_id::create("READY",,get_full_name());

...

   endfunction: new

   `uvm_object_utils(ral_vreg_enet_bd)

endclass : ral_vreg_enet_bd

 

class ral_block_bd extends uvm_reg_block;

  rand ral_vreg_bd bd;

  rand ral_mem_bd_sys_mem sys_mem;

...

   virtual function void build();
      this.default_map = create_map("", 0, 32, UVM_BIG_ENDIAN, 1);
      this.bd = ral_vreg_enet_bd::type_id::create("bd",,get_full_name());
      this.bd.configure(this, , 0, 'h0, 0);

...

      this.sys_mem = ral_mem_enet_bd_sys_mem::type_id::create("sys_mem",,get_full_name());
      this.sys_mem.configure(this, "");
      this.sys_mem.build();
      this.default_map.add_mem(this.sys_mem, `UVM_REG_ADDR_WIDTH'h0, "RW", 0);

 

   endfunction : build

    `uvm_object_utils(ral_block_enet_bd)

endclass : ral_block_enet_bd

 

Thanks in advance.

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+uvm_set_default_sequence usage behavior in UVM 1.2

April 15, 2014, 6:00 am
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I have two sequences seq_a and seq_b that can be run on sequencer.

In my component i have the code to set the default sequence.

Below is the code in component and i am trying to set the default sequence as "seq_b"

 

task run_phase(uvm_phase phase);

uvm_config_db #(uvm_object_wrapper)::set(null, "uvm_test_top.my_sequencer.main_phase", "default_sequence", seq_b::type_id::get());
sequencer.start_phase_sequence(phase);
endtask: run_phase
With this code in component, if i pass the following command lines argument to change the sequence to seq_a: 
 "+uvm_set_default_sequence=*,main_phase,seq_a"

The sequence that runs on sequencer is still seq_b only, it was not modified to seq_a.  

Sequence control from command line works when i comment the default_sequence code in run_phase.

It looks for me that "+uvm_set_default_sequence" can't be used when i am setting the default_sequence inside the run_phase.

It will be good if "+uvm_set_default_sequence" overrides the default_sequence that was set in run_phase. So that it gives more flexibility from command line.

 

Please give your comments on this behavior on UVM 1.2.

 

 

 

 

 
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+uvm_set_default_sequence=*,run_phase is causing two threads to spawn

April 15, 2014, 6:30 am
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I am running the UVM 1.2 examples code given in following link, which are there to demonstrate the UVM 1.2 new features.

 

http://www.edaplayground.com/s/4/1037

 

In the above code, the default sequence code can be controlled from command line with following code.

"+uvm_set_default_sequence=*,main_phase,seq_b"

If i use run_phase instead of main_phase, to control the default sequence, then same sequence will run twice instead of one.

"+uvm_set_default_sequence=*,run_phase,seq_b"

Two sequence threads are getting spawned parallelly, if i use run_phase to control default sequence.

 

I am expecting the behavior should be same whether i use run/main_phase. Not able to figure it out, why different behaviors are seen? 

This behavior is seen with UVM 1.2.

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Many-to-one on a TLM

April 17, 2014, 10:25 am
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Rookie question:

Is it as obvious as it may seem to simply have just the one imp on the consumer side of say a put_port (non-blocking most likely), and multiple producers can connect to that single imp?

 

Yes, they would all be the same item types, and yes they would all be handled the same way.

 

Not the same as an analysis_port.  More like an analysis_port with the traffic flowing the opposite direction. ;)

 

Any issues I may be overlooking or missing?

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The difference between run_phase and main_phase in uvm_component

April 22, 2014, 11:30 pm
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Hi,

 

Could anyone please clarify what's the difference between run_phase and main_phase in uvm_component? What are both do for?

 

Thanks,

Brian

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`uvm_do_with is not working with variable constraint

April 28, 2014, 3:23 am
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Following is the sequence code

 

class basic_sequence extends from uvm_sequence(#sequence_item);

 

sequence_item item;

 

task body()

 

fp1 =fscanf("abc.txt", addr, data);

 

`uvm_do_with(item,{

                               item.addr = addr;

                               item.data = data;

                              });

 

endtask

 

endclass

 

I have constrained addr and data from file reading data. It is not happening with the above code. data_item is getting a random value.

 

 

I have written a user-defined task to solve this problem like below

 

task do_rw(int addr, int data);
  begin
   item = sequence_item::type_id::create("item",,get_full_name());
   item.wr_adr.rand_mode(0); 
   item.wr_dat.rand_mode(0); 
   item.wr_adr = addr;
   item.wr_dat = data;
   start_item(item);
   randomize(if_item);
   finish_item(item);
  end
endtask
 

inplace of uvm_do_with call uder defined do_rw task like below

fp1 = fscanf("abc.txt", addr, data);
while(!eof(fp1) {
do_rw(addr, data);
}

This will work. I used above solution to work. I really don't understand why uvm is not supporting it with uvm_do_with. any answers for fit??

 

Thanks,

Satya

 

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verifying protocol without reference model

May 4, 2014, 2:14 am
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I am new to verification.

 

Now I trying to verify a protocol like TCP/IP  stack(mainly TCP over IP, without UDP, ICMP etc.). 


My first idea is that a golden Reference Model is needed. I generate sequences, send them to DUT through a driver, and monitoring my driver, get each transaction to RM, then I collect the response from both DUT and RM and compare them. But building  such a RM would be very complex.
 
My question is, do I really need a RM? What if I verify my DUT without any RM? 
 
For example, to verify DUT's feature of opening as client, my sequence can simply act as a server and do such routine:
 
1, send OPEN AS CLIENT command to DUT.
2, wait response from DUT, which should be a SYN. if not, assume test fail and exit. 
3, send SYN ACK to DUT.
4, wait response from DUT, which should be an ACK. if not or wrong ACK, assume test fail and exit.
5, end, assume test pass.
 
 
 
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UVM_REG and multiple reset

May 7, 2014, 1:08 am
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Hi,

 

I am testing multiple reset.

 

My testbench is based on UVM_REG and I am using "write()" API to write registers.

If reset is asserted when write() is executed, the next warning occurs.

 

UVM_WARNING (UVM/FLD/SET/BSY) Setting the value of field "xxx" while containing register "yyy" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

 

As I debugged, the error is caused by "m_is_busy" variable of uvm_reg.svh.

While write() is executed "m_is_busy" is set to 1 and set to 0.

 

When reset is asserted, user scenario kills write() operation and reset all registers as calling reg_block.reset().

If reg_block.reset() is executed, mirrored value seems to be reset but desired value does not.

 

And also, if reset is asserted between the time that "m_is_busy" is set to 1 and the time that "m_is_busy" is set to 0, "m_is_busy" remains "1". The same register is accessed later again, the above warning occurs.

 

I think this warning is no effect for simulation result. But I want to clear this warning.

Should user control UVM internal variable such as m_is_busy?

When reset is asserted, what is right that which value the desired value of field has?

How can I clear this warning?

 

Thanks & Regards,

yyn

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Regarding the UVM field automation macros

May 7, 2014, 4:59 am
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Hi,

 

We are planning to use UVM for full chip level verification. Some of the papers and posts recommending against the usage of field automation macros.

Are these macros improved in latest version of UVM (UVM1.1d) for simulation performance and amount of code they generate? Can we use them now?

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Pseudo timing checks in UVC

May 7, 2014, 9:09 am
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Hi everyone,

 

I have a question that is more on the methodology side. Let me describe the issue. For our APB peripherals we have a little deviation from the standard protocol. The protocol mentions that PWDATA must be stable already during the setup phase (first cycle of a transfer), but in order to have a more area optimized implementation of our AHB2APB bridge our designers have declared that PWDATA is valid only during the access phase (second cycle) so that they can set a multicycle path on it. This is a requirement for our peripherals to sample PWDATA only on the second cycle and not before. I'm not really sure what the best way to verify this would be as this seems kind of like doing timing verification.

 

What has up to now been done is to randomize the value of the control signals during the setup phase and then drive PENABLE and PSEL high together with PWDATA (basically a legal access phase). I find this approach clumsy and trying to be overly clever. My idea would have been to drive legal protocol except for PWDATA which I would drive to unknown during the first cycle. This way, if the DUT were to sample the signal during the setup phase, it would sample an unknown value and it would fire up any assertions inside it or in the testbench in case of a readback. This is basically what would happen in a physical system (or?).

 

I would like to know if anybody else has encountered something similar and how they solved the problem.

 

Thanks,

Tudor

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UVM Heartbeat: How does it works?

May 12, 2014, 5:48 am
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Hi,

 

I am using UVM heartbeat in my testbench and defining UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE, so the run time phase will be of type 'uvm_callbacks_objection' instead of 'uvm_objection'.

 

In order to do some end of sim checks, i am waiting for 'phase.wait_for_state(UVM_PHASE_READY_TO_END, UVM_EQ);'

 

Looks like the phase's state is not changing to  'UVM_PHASE_DONE', it is still 'UVM_PHASE_EXECUTING'.  The total objection count is 0.

 

During this time, heartbeat event is getting triggered and test is ending with a fatal msg, which is not expected.

 

 

Configured Hearbeat mode        = UVM_ANY_ACTIVE.

                  Heartbeat_window    = 100000;;

 

 

Snippet from log:

 

The total objection count is 0

Heartbeat  : Triggering an heart beat event at T=  190624 ns

 

....

....

The total objection count is 0

....

....

 

Heartbeat  : Triggering an heart beat event at T=  381249 ns 
The total objection count is 0
 
The total objection count is 0
 
UVM_FATAL @ 381249046875: env [HBFAIL] Did not recieve an update of run on any component since last event trigger at time 190624047000. The list of registered components is:
 
 
Am i missing some thing ?
 
Can some one please help in debugging this.  Thanks.
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uvm_analysis_imp#()::get would be nice

May 22, 2014, 12:47 pm
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It would be really nice to be able to receive TLM messages in some sequences for the purposes of coordinating stimulus with monitored events.

 

I have a solution which gets the job done, but it's not as clean as it should be, and this missing feature feels like a gaping hole in the methodology.

 

I think a very nice solution would be to have uvm_analysis_imp#() class either implement the get() method, or maybe more clearly have a new method called wait_for_write( T t ).

 

You could then extend your sequencer to have a uvm_analysis_imp#(), and use `uvm_declare_p_sequencer() in your sequence to provide access to the analysis port.  Here's a partial example of what the user code would look like:

class ItemSqr extends uvm_sequencer#( Item );
    uvm_analysis_imp#( OtherItem ) other_item_analysis_export;
    // .. rest of class definition
endclass


class TestSeq extends uvm_sequence#( Item );
    `uvm_object_utils( TestSeq )
    `uvm_declare_p_sequencer( ItemSqr )
  
    // ....

    virtual task body( );
        OtherItem t;
        // .. do some transactions
        p_sequencer.other_item_analysis_export.wait_for_write( t );
        // .. do some more transactions
    endtask


endclass

I basically implement this now, but UVM should do it for me.

 

-Ryan

 

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How to delay a sequence from a test

May 27, 2014, 3:19 am
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Hi,

 

I have a sequence running but i want to delay that sequence for 50 clk. How can i do it from the test.

Is reset_phase a good option in the test class? or is their another way out.

 

thanks

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